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JFET active load input stage

机译:JFET有效负载输入级

摘要

An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors, thereby reducing voltage offsets which degrade common mode rejection ratio. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors are supplied with current from current sources independent of the amplifier transistors, and deliver their respective currents to the same resistors which receive the amplifier currents. An output is taken from one of the load transistors without connecting to either of the amplifier transistors.
机译:描述了一种用于运算放大器等的有源负载电路,其提供了改善的共模抑制比和共模电压范围,并减轻了晶体管的饱和和最大压摆率期间的截止问题。来自运算放大器或其他电路的驱动电流直接通过相应的负载电阻传输,从而减少了电压偏移,降低了共模抑制比。同时,运算放大器或类似电路上的绝对电压电平降低,从而增加了共模电压范围。一对有源负载晶体管从独立于放大器晶体管的电流源提供电流,并将它们各自的电流传送到接收放大器电流的相同电阻器。从负载晶体管之一取得输出,而没有连接到任何一个放大晶体管。

著录项

  • 公开/公告号US4687984A

    专利类型

  • 公开/公告日1987-08-18

    原文格式PDF

  • 申请/专利权人 PRECISION MONOLITHICS INC.;

    申请/专利号US19840615996

  • 发明设计人 JAMES R. BUTLER;

    申请日1984-05-31

  • 分类号H03F3/68;

  • 国家 US

  • 入库时间 2022-08-22 07:08:57

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