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JFET active load input stage

机译:JFET有效负载输入级

摘要

An active load circuit for operational amplifiers and the like is described which provides an improved common mode rejection ratio and common mode voltage range, and alleviates transistor saturation and cut off problems during maximum slew rates. Drive currents from the operational amplifier or other circuit are transmitted directly through respective load resistors (R 1, R2), thereby reducing voltage offsets which degrade common mode rejection. At the same time the absolute voltage levels at the operational amplifier or like circuit are reduced, thereby increasing the common mode voltage range. A pair of active load transistors (Q1, Q2) are supplied with current from current sources (15,16) independent of the amplifier transistors (J 1, J2), and deliver their respective currents to the same resistors (R1, R2) which receive the amplifier currents. An output (Q4) is taken from one of the load transistors (Q1, Q2) without connecting to either of the amplifier transistors (J1, J2).
机译:描述了一种用于运算放大器等的有源负载电路,其提供了改善的共模抑制比和共模电压范围,并减轻了晶体管的饱和和最大压摆率期间的截止问题。来自运算放大器或其他电路的驱动电流直接通过各自的负载电阻(R 1,R 2)传输,从而减少了电压偏移,降低了共模抑制性能。同时,运算放大器或类似电路上的绝对电压电平降低,从而增加了共模电压范围。一对有源负载晶体管(Q1,Q2)从电流源(15,16)获得电流,电流源(15,16)与放大器晶体管(J1,J2)无关,并将它们各自的电流传送到相同的电阻(R1,R2),接收放大器电流。从负载晶体管(Q1,Q2)中的一个取得输出(Q4),而不连接到任何一个放大器晶体管(J1,J2)。

著录项

  • 公开/公告号EP0164182B1

    专利类型

  • 公开/公告日1988-12-28

    原文格式PDF

  • 申请/专利权人 PRECISION MONOLITHICS INC.;

    申请/专利号EP19850301899

  • 发明设计人 BUTLER JAMES R.;

    申请日1985-03-19

  • 分类号H03F3/45;

  • 国家 EP

  • 入库时间 2022-08-22 06:35:24

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