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DEBUG SYSTEM FOR PARALLEL PROGRAM

机译:并行程序的调试系统

摘要

PURPOSE:To grasp the states of plural processors just with a single terminal equipment by incorporating a debug monitor into a host computer to ensure the unitary control of the debugger main bodies stored in all programs when plural programs that work in parallel with each other via plural processors are debugged. CONSTITUTION:A debug file input/output instruction, a defining instruction and a debug area setting instruction are supplied to a terminal equipment 14 regardless of the operations of processors 21-25 and the memory contents. Under such conditions, only a debug monitor 13 incorporated in a host computer 11 performs the processing and requests a user to deliver the next debug instruction. A monitor 13 informs the debug instruction supplied to the equipment 14 to the corresponding processor as long as said debug instruction is equal to a designating instruction for the number of the processor to be noticed. Then the monitor 13 turns on the flag of a debugger main body 31 put into the processor and reports the end of operation to the monitor 13. The monitor 13 displays the processor number designated to the equipment 14 and a list connected to said number and requests the next debug instruction to the user to repeat this action.
机译:目的:通过将调试监控器集成到主机中,仅使用一个终端设备即可掌握多个处理器的状态,以确保当多个程序通过多个并行运行时,统一存储在所有程序中的调试器主体的控制处理器已调试。组成:调试文件输入/输出指令,定义指令和调试区域设置指令被提供给终端设备14,而与处理器21-25的操作和存储内容无关。在这样的条件下,仅主机11中内置的调试监视器13执行该处理并请求用户传递下一个调试指令。监视器13将提供给设备14的调试指令通知给相应的处理器,只要所述调试指令等于要注意的处理器编号的指定指令即可。然后,监视器13打开置于处理器中的调试器主体31的标志,并向监视器13报告操作的结束。监视器13显示指定给设备14的处理器编号以及与该编号连接的列表并请求用户的下一条调试指令将重复此操作。

著录项

  • 公开/公告号JPS63177231A

    专利类型

  • 公开/公告日1988-07-21

    原文格式PDF

  • 申请/专利权人 NIPPON TELEGR & TELEPH CORP NTT;

    申请/专利号JP19870008756

  • 发明设计人 MOMOI SHIGEHARU;MIZUGAKI AKIO;

    申请日1987-01-17

  • 分类号G06F11/28;G06F15/16;G06F15/177;

  • 国家 JP

  • 入库时间 2022-08-22 07:06:03

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