首页> 外国专利> TEMPERATURE COMPENSATION HYSTERESIS BUFFER AND METHOD FOR REGULATING HYSTERESIS REFERENCE LEVEL WITH THE TEMPERATURECOMPENSATING HYSTERESIS BUFFER

TEMPERATURE COMPENSATION HYSTERESIS BUFFER AND METHOD FOR REGULATING HYSTERESIS REFERENCE LEVEL WITH THE TEMPERATURECOMPENSATING HYSTERESIS BUFFER

机译:温度补偿迟滞缓冲垫和利用温度补偿迟滞缓冲垫调节迟滞参考水平的方法

摘要

A hysteresis circuit is disclosed in which a first signal path, including a hysteresis feedback loop, is separate from a second signal path that is used to carry data. When the signal input to the hysteresis circuit (also referred to hereinafter as the "input signal") crosses a first preselected hysteresis reference (of "threshold") level, the hysteresis feedback loop, which includes threshold adjustments means, will cause a change in the threshold from the first preselected level to a second preselected level. This adjustment of threshold level will take place in parallel with the data being propagated to the output over said separate second signal path. A subsequent crossing of the second preselected threshold level by said input signal will cause the first threshold level to be reset and so on. According to the preferred embodiment of the invention, the threshold adjustment means included in said first signal path further includes a temperature compensation string, current switching means and means which act as an anti-hysteresis killer to speed up the operation of the hysteresis circuit. This novel combination is operative to assure a preselected minimum hysteresis window over the 200 DEG C temperature range between -55 DEG C and 155 DEG C, and renders the hysteresis circuit suitable for use in both military applications and other hostile environments. Furthermore, according to the preferred embodiment of the invention, the hysteresis circuit has a PNP input stage to reduce IIL and acordingly improve the input characteristics of the circuit, particularly fan-in. The circuit also features a low ICC and is designed to be self-compensating with respect to manufacturing disparities inherent in components used to fabricate the circuit itself.
机译:公开了一种磁滞电路,其中包括磁滞反馈回路的第一信号路径与用于承载数据的第二信号路径分开。当输入到磁滞电路的信号(以下也称为“输入信号”)越过第一预选的磁滞基准(“阈值”)电平时,包括阈值调整装置的磁滞反馈回路将引起从第一预选等级到第二预选等级的阈值。阈值电平的这种调整将与通过所述单独的第二信号路径传播到输出的数据并行进行。所述输入信号的第二预选阈值电平的随后越过将导致第一阈值电平被重置,依此类推。根据本发明的优选实施例,包括在所述第一信号路径中的阈值调节装置还包括温度补偿串,电流切换装置和用作防滞后装置以加速滞后电路的操作的装置。这种新颖的组合可确保在-55℃至155℃之间的200℃温度范围内预先选定的最小磁滞窗口,并使磁滞电路适用于军事应用和其他恶劣环境。此外,根据本发明的优选实施例,磁滞电路具有PNP输入级,以减小IIL并相应地改善电路的输入特性,特别是扇入。该电路还具有低ICC的特点,并设计为可自我补偿,以补偿用于制造电路本身的组件固有的制造差异。

著录项

  • 公开/公告号JPS6359018A

    专利类型

  • 公开/公告日1988-03-14

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICDS INC;

    申请/专利号JP19870206212

  • 发明设计人 MAATEIN SHIEN;

    申请日1987-08-19

  • 分类号H03K3/2897;H03K3/011;H03K3/0233;H03K3/037;

  • 国家 JP

  • 入库时间 2022-08-22 07:04:38

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