PURPOSE:To reduce delay in a processing due to the collision of buses, by separating a memory into plural banks, and preparing a multiple system of buses, in the shared memory device of a LISP machine in a computer architecture. CONSTITUTION:A memory is divided, and a cell block I is a memory block in which the cell exists, and a tag block II is a block for an area to put a mark, and a control block III is the block for the flag of an inseparable operation, or a working area, and a hardware stack block IV is the block in which a hardware stack exists. Each block is connected with each other through respective processor, and bus arbiter. When an L.P.U. (list processing unit) accesses to a cell memory, the bus arbiter 3 connects the L.P.U. to the cell memory by a bus request signal. At this time, and simultaneously, it is possible to access to the hardware stack by a GCU (garbage collection unit) 1, and to access to a control memory by a GCU2.
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