Adder circuit using decimal 1-out-of-10 code - has main adder, auxiliary circuit with dual half adder, and number alteration stage

摘要

The adder circuit has an alteration stage which allows the obtained number to be fed on unaltered or to be raised by 5 when it lies between 0 and 4, or to be reduced by 5 when it lies between 5 and 9. The main circuit comprises 5 or 6 individual adders, with prior processing of the value 5 via a dual half-adder and an auxiliary circuit without a dual half-adder. Each adder pref. comprises as OR circuit with 2 inputs and as AND circuit with 2 inputs and is controlled by the count value 2. ADVANTAGE - Allows number of adders required for main adder circuit to be reduced.