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Logic circuit of detection for a system of synchronous transmission of data symbols and the control of a ternary intersymbol interference type class 1 partial response (n = 2

机译:数据符号同步传输系统的检测逻辑电路和三级符号间干扰类型1部分响应(n = 2)的控制

摘要

This logic circuit of the detection makes it possible to find the value of a symbol ternary 0, 1 is converted into a signal has five levels 0, 1, 2 by a transmission type classe1n2 partial response. designed exclusively in the binary logic circuits, it is used as a result of a comparator has four thresholds 1 issuing the value of the level of reception by means of four binary signals: two overtake positive of the thresholds positive outer and intermediate b, b and two thresholds overtake negative negative outer and intermediate b, b and issued the values of the symbols ternary detected in the form of two binary components available on the outputs (t, t), stored, the time of a symbol in the flip-flops 104, 105 and generated both with the aid of a combinational logic circuits similar to the basis of logic gates of the type "or" and "or" 108, 109, 110 - 111, 112, 113.
机译:该检测的逻辑电路使得可以找到符号三元的值0、1,通过传输类型classe1n2部分响应将其转换为具有五个电平0、1、2的信号。它专门用于二进制逻辑电路中,它作为比较器的结果使用,具有四个阈值1通过四个二进制信号发出接收电平的值:两个超越阈值的正值,正外部b,b和b两个阈值超过负的负的外部和中间的b,b,并以在输出端(t,t)上可用的两个二进制分量的形式发布检测到的三进制符号的值,存储在触发器104中符号的时间,105和105借助组合逻辑电路生成,该组合逻辑电路类似于类型为“或”和“或”的逻辑门108、109、110-111、112、113。

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