Subnanosecond programmable phase shifter for a high frequency digital PLL

摘要

A circuit for producing a programmable phase shift of clock pulses in response to the data on a group of control lines. The circuit includes a ramp generator stage coupled to drive a comparator stage which has a reference potential input determined by the control line data. The phase shift can be employed to produce a series of subnanosecond delay increments on the clock pulses and is useful in the fine adjustment of a digital phase lock loop.