APPLICATION OF DEEP JUNCTION NON-SELF MATCHING TYPE TRANSISTOR FOR INHIBITING HOT CARRIER

摘要

PURPOSE: To prevent deterioration in a device due to hot carrier injection and enhance reliability for a long time, by utilizing steps for the manufacture of MOS capacitors, and simultaneously causing deep-junction source and drain diffusion useful for the suppression of hot carriers in a short-channel MOS transistor. CONSTITUTION: A silicon dioxide layer 14 is etched to expose the surface area of a p-type substrate 12. Phosphorus atoms as n-type dopant is implanted in the substrate 12 through the exposed surface area to form a first n+ diffusion region 16 that functions as the lower plate of a MOS capacitor, and further form a second n+ diffusion region 18 and a third n+ diffusion region 20 that function as the source region and drain region of a deep-junction, non-self- aligned NMOS device. Then a gate oxide layer 22 is formed, and the n-type dopant is simultaneously diffused in the lateral direction. As a result the effective channel length between the regions 18 and 20 becomes approx. 3.5 microns. Thereafter, a polysilicon layer is formed on the gate oxide layer to define the upper plate 24 of the MOS capacitor and the non-self-aligned gate 26 of the deep-junction NMOS device.