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CELL STRUCTURED DIGITAL MULTIPLIER OF SEMI-SYSTOLIC CONSTRUCTION

机译:半收缩构造的细胞结构数字倍增器

摘要

A digital multiplier which has cells arranged in a plurality of rows and columns wherein the rows are assigned to different groups of partial product bits. Sum paths and carry paths are provided which connect the individual cells to each other and at their ends emit signals from which the product bits are formed. The multiplicand bits are stored intermediately together with the sum and carry signals formed in a row and are simultaneously forwarded to the next row in accordance with a pipelining process. It is desired to obtained the least possible delay in feeding a multiplier bit into all the cells of a row so as to achieve short range transit time of the signals between the output of two consecutive rows and this is achieved with a logic link element which is used to form a partial product bit which is contained in a cell which proceeds the row and in which this partial product bit is added to sum signals and carry signals. One of the cells of the following row contains a full adder which is connected to the output of the logic link with a connection line which is provided with a shift register stage. The invention can be used for integrated circuit for digital data processing.
机译:一种数字乘法器,其单元以多个行和列排列,其中,行被分配给部分乘积位的不同组。提供了求和路径和进位路径,它们将各个单元相互连接,并在其端部发出信号,由此形成乘积位。被乘数位与和一起存储在中间,并携带形成一行的信号,并根据流水线处理将其同时转发到下一行。希望在将乘法器位馈送到一行的所有单元中时获得最小的延迟,以实现两个连续行的输出之间信号的短距离传输时间,这是通过逻辑链接元件实现的。用于形成部分乘积比特,该部分乘积比特包含在行继续的单元中,并且在该单元中将该部分乘积比特相加以求和信号并携带信号。下一行的单元之一包含一个全加法器,该加法器通过连接线连接到逻辑链路的输出,该连接线具有移位寄存器级。本发明可以用于数字数据处理的集成电路。

著录项

  • 公开/公告号AU581924B2

    专利类型

  • 公开/公告日1989-03-09

    原文格式PDF

  • 申请/专利权人 SIEMENS AKTIENGESELLSCHAFT;

    申请/专利号AU19850047489

  • 发明设计人 TOBIAS NOLL;

    申请日1985-09-16

  • 分类号G06F7/52;

  • 国家 AU

  • 入库时间 2022-08-22 06:35:48

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