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Multiple output field effect transistor logic

机译:多输出场效应晶体管逻辑

摘要

In MOS logic circuits with a non-complementary circuit structure (for example, dynamic CMOS), a prior art logic gate generated only a single output signal. However, the logic tree often implements multiple functions, with one function being contained within another function. With prior art logic, if two or more of these functions are needed as separate available output signals, they have to be implemented in several separate gates. The present invention utilizes intermediate functions (10) within the logic tree, providing gates having multiple outputs. Therefore, the present invention reduces the replication of circuitry, thus reducing circuit device count. The advantages include reduced integrated circuit chip area, speed improvement, and power savings, due to the reduction of device count and the corresponding reduction in wire lengths and output loading, etc.
机译:在具有非互补电路结构的MOS逻辑电路(例如,动态CMOS)中,现有技术的逻辑门仅产生单个输出信号。但是,逻辑树通常实现多个功能,一个功能包含在另一个功能中。利用现有技术的逻辑,如果需要这些功能中的两个或更多个作为单独的可用输出信号,则必须在几个单独的门中实现它们。本发明利用逻辑树内的中间功能(10),提供具有多个输出的门。因此,本发明减少了电路的复制,从而减少了电路装置的数量。优点包括由于减少了设备数量并相应减少了导线长度和输出负载等而减少了集成电路芯片的面积,提高了速度并节省了功率。

著录项

  • 公开/公告号EP0320111A2

    专利类型

  • 公开/公告日1989-06-14

    原文格式PDF

  • 申请/专利权人 AT&T CORP.;

    申请/专利号EP19880310342

  • 发明设计人 HWANG INSEOK STEVEN;

    申请日1988-11-03

  • 分类号H03K19/096;

  • 国家 EP

  • 入库时间 2022-08-22 06:34:07

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