Amplifier arrangement for an adaptive reduction of an unwanted d. c. offset in an input signal and an AM receiver using same

摘要

An amplifier arrangement for reducing an unwanted d.c. offset of an amplitude-varying input signal, has a threshold circuit (A.sub.3, B. sub.3) and an amplifier stage (A.sub.1, B.sub.1) coupled thereto, which threshold circuit (A.sub.3, B.sub.3) is provided with a bistable trigger circuit (A.sub.4, B.sub.4). This bistable trigger circuit (A.sub.4, B.sub. 4) reduces the d.c. level of the input signal or output signal of the amplifier stage (A.sub.1, B.sub.1) in a steplike manner when this d.c. level increases. The bistable trigger circuit (A.sub.4, B.sub.4) has a hysteresis which is larger than the maximum amplitude variation of the input signal as a result of the desired signal component, so that a linear amplification of this desired signal component is possible and, in the case of a non-varying d.c. level, variations of the input signal due to the desired signal component cannot give rise to a d.c. reduction. This amplifier arrangement may be used in a phase-locked loop of a directly mixing synchronous AM receiver, which phase-locked loop is used for generating a synchronous local carrier in order to increase the input dynamic range of the receiver.