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High-speed refreshing rechnique for highly-integrated random- access memory
High-speed refreshing rechnique for highly-integrated random- access memory
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机译:高速刷新技术,用于高度集成的随机存取存储器
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摘要
A divided-bit line type dynamic random-access memory is disclosed which has parallel main bit line pairs in each of which sub-bit line pairs are provided to be electrically parallel with each other. Parallel word lines are provided on the substrate to insulatively cross the sub- bit line pairs. Memory cells are connected to crossing points of the sub- bit line pairs and the word lines. Main sense amplifiers are respectively connected to the main bit line pairs, sub-sense amplifiers are respectively connected to the sub-bit line pairs. A specific refreshing technique is utilized, according to which, when a refreshing operation is executed in a refreshing mode of the memory, the same number of word lines as that of sub-bit line pairs provided in each main-bit line pair are simultaneously selected, and the sub-sense amplifiers are activated to refresh together the memory cells which are connected to the work lines thus selected.
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