首页> 外国专利> Functional dividable multiplier array circuit for multiplication of full words or simultaneous multiplication of two half words

Functional dividable multiplier array circuit for multiplication of full words or simultaneous multiplication of two half words

机译:功能可分割乘法器阵列电路,用于全字乘法或两个半字的同时乘法

摘要

A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non- division mode and which operate as the code cells in the division mode. Further, the cell array blocks include selectors to supply an inactive value to the cells to perform the multiplication of the upper bits of the multiplicand and the lower bits of the multiplier and to the cells to perform the multiplication of the lower bits of the multiplicand and the upper bits of the multiplier in such a manner that the cell array blocks can supply the multiplicand and its inverted data to the cells constituting the cell array blocks in the non-division mode and can simultaneously execute two series of multiplications in the division mode.
机译:一种乘法器阵列电路,包括用于根据布斯算法对乘法器进行解码的解码器;单元阵列块,用于接收来自解码器和被乘数的选择信号,并根据布斯算法执行被乘数和乘数的相乘;一个加法器,用于根据单元阵列块的输出获得最终产品。为了实现功能上的划分操作,单元阵列块包括在非划分模式下用作基本单元并且在划分模式下用作代码单元的复杂单元。此外,单元阵列块包括选择器,以将无效值提供给单元以执行被乘数的高位和乘法器的低位的相乘,并提供给单元以执行被乘数的低位和乘法器的低位的相乘。乘法器的高位以这样一种方式,即单元阵列块可以在非除法模式下将被乘数及其倒相数据提供给构成单元阵列块的单元,并且可以在除法模式下同时执行两个系列的乘法。

著录项

  • 公开/公告号US4825401A

    专利类型

  • 公开/公告日1989-04-25

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号US19870025201

  • 发明设计人 NOBUYUKI IKUMI;

    申请日1987-03-12

  • 分类号G06F7/52;

  • 国家 US

  • 入库时间 2022-08-22 06:28:13

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