SYNCHRONIZING STEP-OUT DETECTION CIRCUIT FOR PHASE LOCKED LOOP CIRCUIT

摘要

PURPOSE:To detect the synchronizing step-out of a phase locked loop circuit (PLL circuit) by providing an AND circuit ANDing the output of 1/m and 1/n frequency dividers and a flip-flop set by the output of the AND circuit. CONSTITUTION:A phase comparator 4 and a voltage controlled oscillator 2, when they are normal, apply phase locking in a range where the output clocks of a 1/m frequency divider 1 and the output clock of a 1/n frequency divider 3 are not overlapped and the output of an AND circuit 5 is at an L level. On the other hand, when the synchronizing step-out takes place and the output clock of the 1/m frequency divider 1 and the output clock of the 1/n frequency divider 5 are overlapped, both outputs are simultaneously at an H level, and the output of the AND circuit 5 goes to an H level, then a flip flop is set and the signal that the synchronizing step-out is detected is outputted. Thus since the synchronizing step-out can be detected when the PLL circuits is faulty and the synchronizing step-out is generated, the fault is found out early and the maintenance performance is improved.