PURPOSE: To obtain an adder giving a minimum gate delay by using the complementary MOS technique and using plural same 4-bit slice blocks to simplify the layout. CONSTITUTION: In the case of a 32-bit adder, blocks 10 to 17 receive four propagation signals Pn, generation signals Gn, and a carry-in signal and supply sum total, carry-out, block propagation, and block generation signals. Blocks 10 to 17 are connected in series, and the carry output terminal of one block is connected to the carry input terminal of the next block, and blocks are divided into groups. The carry-in signal is connected through transistors TRs 28, 30, and 33, and the propagation time is determined by the delay in three path gates in the 32-bit adder because they are all of TRs in the carry chain where the carry signal passes. Thus, the delay is shortened to increase the operation speed.
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