Large-scale EPROM memory with checkerboard pattern, improved coupling factor and redundancy

摘要

The present invention relates to an electrically programmable non-volatile memory composed of a network of word lines lm2 extending along a first direction of the row, and the bit lines lb2 to lb4 extending along a second direction of the column. A conductive zone 25 formed by a second level of polycrystalline silicon is in contact and covers the floating gate 23 of each transistor projecting in the direction of the rows. The conductive zone 25 in each transistor is in front of the word line connected to the transistor, this word line corresponding to the location of the conductive zones, to the control gate 28.