The system being usable at the IBM-PC compatible computer comprises; a parallel interface (PPI) having A, B, C and D port receiving digital conversion data and providing A/D converter (ADC) start signal on ADC channel selection signal, and converted digital data; an A/D converter (ADC) started with B port signal of the PPI applying the digital data converted from analog signal of sensor and interface circuit to A port of the PPI, and providing an interrupt signal (IRQ2) to I/O slot (IOS) through a terminal (EOC) after completing the data conversion; a counter/timer (CTC) counting the speed check input pulse applied to selected channel (INO) to provide the accessed data to host computer at every sampling period; and an address decoder logic (ADC) applying a chip selecting signal to the CTC and PPI.
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