CCD delay line with buried CC element - has input bias voltage adjuster for clamping signal to be delayed and its supply to delay line

摘要

The delay line forms chrominance and luminance signals from a video signal detected by a solid state scanner. The biasing voltage control is carried out with high precision, even under mfg. tolerances and temp. variations. The delay line contains a first standard register and a reference register, each with a transmission path, formed by a buried CCD. Two different constant voltages are supplied to the sync. peak biasing voltage point in input section of the reference register. The switching of the two control gate electrodes, which are formed between the biasing voltage point and the transmission path of the reference register, is so carried out that a signal charge, stored in agreement with the inner potential level difference, is used as the transmission signal. ADVANTAGE - Precise biasing voltage control in very wide range.