Arithmetically computed motor hunt compensation for flying spot scanners

摘要

An arithmetic frequency synthesizer having an accumulator for recursively accumulating a R-bit long input word at a predetermined reference frequency to generate a variable frequency bit clock for a flying spot scanner with a rotating polygon for cyclically scanning an intensity modulated light beam across a photosensitive recording medium includes means for arithmetically modulating the value of the accumulator input word on a scan cycle-by-scan cycle basis for adjusting the bit clock frequency to compensate for polygon motor hunt errors. There is a counter which is incremented or decremented during each scan cycle at a frequency which is scaled to the reference frequency, whereby the count accumulated by the counter during each scan cycle is a measure of the average angular velocity of the polygon during that cycle. This count is offset by a calibrated R-bit long bias value; either by preloading the bias value, into the counter at the start of each scan cycle or by summing the bias value, in whole or part, with the accumulated count. The bias value is selected so that offset count or the averaged offset count accumulated during one or more earlier scan cycles, respectively, defines the modulated input word value, adjusts the frequency of the bit clock to compensate substantially for the average motor hunt occurring during the earlier scan cycle or cycles.