PURPOSE:To ensure high speed synchronization among pipeline computers with simple hardware by providing a holding means to each stage of plural instruction pipelines of the computers. CONSTITUTION:A 1st instruction pipeline 10 includes the 1st - 3rd stages 111 - 113, and a 2nd instruction pipeline 11 includes the 1st - 4th stages 121 - 124. An instruction 1 is simultaneously supplied to both pipelines 10 and 11 through an instruction supply part 20. Then the synchronization is secured between the stages of a master instruction pipeline and a slave one and the progress of the slave instruction pipeline is controlled based on the control signal of the master instruction pipeline, the value of a state holding element means contained in a state holding means which holds the instruction progress state of the master instruction pipeline provided to the slave instruction pipeline, and the control signal of the slave instruction pipeline. In such constitution, the high speed synchronization is secured among pipeline computers with use of small hardware.
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