device to correct the paradoxes of successive datenbloecken.

摘要

A deskew processor includes first and second memory units (34,36). Write control circuits load successive data into respective memory units as it is received, and a read control circuit reads the data out of the memory units into a data selector circuit (60) as determined by a data selector control circuit (46), which delays read out of data via the data selector circuit until the previous data is completely read, thereby deskewing the successive data.