APPARATUS AND METHOD FOR AN EXTENDED ARITHMETIC LOGIC UNIT FOR EXPEDITING SELECTED FLOATING POINT OPERATIONS

摘要

APPARATUS AND METHOD FOR AN EXTENDEDARITHMETIC LOGIC UNIT FOR EXPEDITINGSELECTED FLOATING POINT OPERATIONSABSTRACTApparatus and method are described for expediting thealignment of the fraction portion of operands in thefloating point operations. The alignment is performed inthe arithmetic logic unit where the argument of theoperand A exponent is subtracted from the argument of theoperand B exponent. Because the result B-A can be anegative quantity, the result A-B can also be required.The arithmetic logic unit of the present inventionprovides additional apparatus for simultaneouslydetermining B-A and A-B. The additional apparatusincludes components in the propagate bit and generate bitcell for determining an auxiliary generate bit; anadditional carry-chain array for combining the carry-insignal, the propagate bit and the auxiliary generate bit;and selection circuits for selecting the appropriateresult.