Digital signal monitoring circuit - uses clock pulse signal as digital signal, and phase control circuit

摘要

The circuitry has two D flip-flops with inputs for a first clock pulse signal (t1), which has the same bit train frequency as the digital signal (d). The circuitry has a control circuit (3) for phase adjustment of the digital signal to that of the first clock pulse signal, in dependence on the phase advance. The first clock pulse signal is supplied to the first D flip-flop (1) via an inverter (5), and to the second D flip-flop (2) directly. The digital signal is fed to the first flip-flop D input. A switch, actuated by the control circuit feeds the digital signal directly to the second flip-flop D input, or couples first flip-flop Q output to second flip-flop D input. USE/ADVANTAGE - For high integration density chip testing, with digital signal phase correction.