Detecting redundant circuit in logic circuit - detecting coincidence between results of simulations with and without pseudo-errors

摘要

The arrangement for detecting redundant circuits in logic circuits contains a logic simulator which performs a first logic simulation in the logic circuit using predefined test data to produce an output data set. A pseudo-error is applied to a selected internal node of the logic circuit. A further logic simulation is condcuted for the logic circuit contg. the pseudo-error. Coincidence between the data produced by the two seimulators is detected to enable identification of the redundant circuit. ADVANTAGE - Enables optimal design of logic circuits and complete location of faults in designed circuit.