Internal circuit for ultra-fast extensive writing for testing dynamic random-access memory

摘要

This circuit, which is arranged in a memory circuit comprising a plurality of detection amplifiers, a plurality of memory cells and a plurality of MOS transistors, comprises: - equalising and linking means 5, including a plurality of assemblies each comprising an MOS equalising transistor M6 and two MOS linking transistors M7, M8, which are placed on two bit lines B/L, B/L each connected to a detection amplifier S1; - means of linking to nodes 4, by which the two bit lines B/L, B/L are connected to two nodes FBL, FBL, for each memory cell block accessed via a selected word line W/L1; W/L2; and - means of processing the write signal 3, for delivering a differential voltage to the means of linking to the nodes when a datum is written to the memory cell MS1, MS5. IMAGE