Method and apparatus for eliminating clockskew race condition errors

摘要

A method and apparatus in an integrated circuit having a plurality of distinct circuit modules which eliminates undesired effects of clock skewing when a common system clock is used. The same phase of the same system clock is used by both a transmitting circuit module and a receiving circuit module when data is communicated between two circuit modules. The receiving circuit module has an input portion having a first transistor clocked by the same phase of the same system clock, a latch and a second transistor. The latch and second transistor are clocked by a complement of the same phase of the system clock.