CMOS TTL input buffer using a ratioed inverter with a threshold voltage adjusted N channel field effect transistor

摘要

The invention applies a weak forward bias to the body of the NFET transistor of a PFET-NFET TTL inverter buffer circuit to lower the NFET threshold voltage by about 0.45 volts, as a result of 1.5&mgr; amps of body-source current providing a body to source voltage of about 0.5 volts to achieve a near ideal switch point of 1.45 volts under nominal conditions. Also a modified inverter circuit with biasing source, two diodes for trip voltage of 1.4 volts and a comparator constitute a central bias generator for supplying proper bias to the body of the NFETs of a plurality of TTL input buffers.