OPTIMIZING METHOD FOR PROPAGATION DELAY OF COMBINATIONAL LOGIC CIRCUIT

摘要

PURPOSE:To present a propagation delay optimizing method for a combinational logic circuit which roughly optimizes logic circuits and minimizes the sacrifice related to the area cost. CONSTITUTION:The propagation delay of a multistage combinational logic circuit consisting of AND, OR, NAND, NOR, and NOT fundamental logic gates is optimized by Boolean techniques, and the area is optimized by the Boolean techniques without degrading the propagation delay, and technology mapping is performed to locally optimize the propagation delay. Boolean techniques powerfull for large-scale conversion of the circuit structure are used in two first optimizing steps.