PURPOSE:To reduce the influence of a fault occurred in a device by attaining the retrial of an instruction at occurrence of a hardware fault if no coincidence is secured between a register to be loaded and a register used for address qualification of the load instruction of the register at execution of the load instructions of plural registers. CONSTITUTION:A detection means 5 detects that the instruction to be executed indicates the load of plural instructions, and a comparison means 28 detects the coincidence between a register to which the executing result of the instruction is written and the register used for address qualification of the instruction. Then it is decided whether the retrial of the instruction should be carried out or not in accordance with the result of the means 28 while the means 5 is detecting the load instructions of plural registers in response to the occurrence of a hardware fault. Thus it is possible to minimize the influence against the execution of an instruction at occurrence of a fault of a device and to improve the reliability in an instruction retrial processing system.
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