Logic gate circuit with limited transient bounce in potential of the internal voltage supply lines

摘要

A logic gate circuit of TTL, ECL or other configuration, having an output stage including at least one transistor (Q2,Q4) and a control transistor (Q3) which switches the output stage to either a low or high conductive state in accordance with an input logic control signal (VIN) supplied to the control transistor (Q3). In order to limit the transient change in potential of the internal voltage supply lines (INT.VCC,INT.GND) of the logic circuit relative to the external voltage supply (VCC(+),EXT.GND) to which they are connected, which occurs during logic state transitions, the base-emitter path of the output transistor (Q2,Q4) is shunted by the collector-emitter path of a current bypass transistor (Q6) the base of which is driven by the control transistor (Q3). The output transistor (Q2,Q4) may be a composite equivalent transistor formed by a Darlington-connected pair of transistors, and the bypass transistor may itself be such a composite transistor. With increasing collector current of the output transistor (Q2,Q4) an increasing proportion of the base drive current supplied thereto by the control transistor (Q3) is diverted by the current bypass transistor (Q6), thereby limiting the maximum collector current of the output transistor (Q2,Q4) and consequently limiting the aforesaid transient change or "bounce" in potential of the internal supply lines (INT.VCC,INT.GND) relative to the external voltage supply.