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Data acquisition systems with programmable bit-serial digital signal processors

机译:带有可编程位串行数字信号处理器的数据采集系统

摘要

A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.
机译:可以与用于产生相应的传感器输出信号的多个传感器结合使用的单片集成电路,该单片集成电路包括用于将每个传感器输出信号转换成位串行数字格式的装置,以及一些包括位的初始处理电路。 -串行乘加处理器。该处理器包括:位串行数字乘法器,用于将位串行形式的第一数字处理器输入信号与第二数字处理器输入信号相乘,以生成数字乘积信号;数字加法器,用于将第三数字处理器输入信号与数字相加。用于产生数字和信号的乘积信号,以及用于向数字处理器输出信号提供与所述数字和信号的比特相对应的比特的装置。存储器系统提供用于存储程序指令的存储器,用于存储第二数字处理器输入信号的连续值的存储器,用于存储第三数字处理器输入信号的连续值的存储器,以及用于存储写入时的数字处理器输出信号的连续值的存储器进入内存系统。可以从传感器输出信号中选择第一数字处理器输入信号,以转换为比特串行数字格式。至少在选定的时间从存储系统读取施加到位串行乘法加法处理器的第二数字处理器输入信号,以及施加到位串行乘法加法处理器的第三数字处理器输入信号。控制器以预定顺序从存储器中检索用于存储程序指令的存储程序指令,并生成用于至少控制存储系统的读取和写入以及选择第一数字处理器输入信号的控制信号。

著录项

  • 公开/公告号EP0498953A2

    专利类型

  • 公开/公告日1992-08-19

    原文格式PDF

  • 申请/专利权人 YOKOGAWA ELECTRIC CORPORATION;

    申请/专利号EP19910120966

  • 发明设计人 GARVERICK STEVEN LEE;FUJINO KENJI;

    申请日1991-12-06

  • 分类号G06F15/78;G01R21/133;G06F7/544;G06F15/31;

  • 国家 EP

  • 入库时间 2022-08-22 05:29:05

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