Interference pulse elimination circuit for data lines - provides rest signal level in critical interference condition along data line

摘要

The circuit (S) comprises 2 pluggable modules (BG1, 2), each with its own voltage supply (SP1, SP2), coupled via at least one data line (DL). The first module (BG1) has a microprocessor (MP), a line driver (LT), and a voltage monitor (WD). The second module (BG2) comprises a pulse evaluator (PB), coupled at its input to the microprocessor output via the line driver and the data line. The critical interference condition, e.g. switching one module, is detected by the voltage monitor to allow a defined rest signal level to be provided along the data line, with simultaneous low-ohmic coupling of the input (PBE) of the pulse evaluator to earth via a resistor (R). USE/ADVANTAGE - For data processing networks, with defined rest signal level for both modules.