Modelling of digital elements within simulation process - is based around shift register chain for simulating performance of system

摘要

Digital elements (BE1-BEn) are combined with a shift register (SRK) as a combinational network for modelling a digital circuit. Activation signals are provided by a signal generator (ZG) and data input (D1) and output (D0) is provided by a data memory (D5). The memory is subdivided into a source data section (SD), response data section (RD) and a test access port control (TAP) section. The cycle of the system to provide simulation of the circuit is provided by a workstation (WS) operating with an address memory. ADVANTAGE - Used for circuit simulation in prototype development.