Clock signal circuit for communications system - has control input of VCO supplied with required output of voltage comparator in dependence on master or slave clock operating mode

摘要

The clock signal circuit provides clock signals (tfs) synchronised in frequency with different reference clock signals (tnr,tr,tpr). Each of the latter is supplied to one input (E1) of a respective phase comparator (PVE1..PVE3), the second input of each of the latter receiving the output of a voltage-controlled oscillator (VCO) providing the output clock signal (tfs). The control input of the voltage-controlled oscillator (VCO) is supplied with a required voltage comparator output signal, in dependence on the required operating mode. ADVANTAGE - Allows switching between master and slave clock modes.