首页> 外国专利> Sensing path arrangement for test circuits, e.g. for testing RAM(s) - has two groups of registers in series with controller managing priority of shift operation of first gp.

Sensing path arrangement for test circuits, e.g. for testing RAM(s) - has two groups of registers in series with controller managing priority of shift operation of first gp.

机译:测试电路的传感路径布置用于测试RAM的-具有两组与控制器串联的寄存器,用于管理第一个GP的移位操作的优先级。

摘要

A sensing path arrangement contains a first sensing register group (10) with a number of first sensing registers connected in series, a second group (20, 30) connected in series with the output of the first group and with registers in series and a controller (60). The controller regulates the first and second groups of registers so that the second group's shift operation is interrupted and the first group's shift operation is carried out. It applies a shift clock signal to the first group and applies a clock signal to the second group depending on a defined control signal. ADVANTAGE - wiring of arrangement is simplified and testing efficiency increased.
机译:感测路径布置包括第一感测寄存器组(10),其具有多个串联的第一感测寄存器,第二组(20、30),其与第一组的输出串联并且与寄存器串联,以及控制器(60)。控制器调节第一和第二组寄存器,以便中断第二组的移位操作并执行第一组的移位操作。它根据定义的控制信号将移位时钟信号应用于第一组,并将时钟信号应用于第二组。优点-简化了布线,提高了测试效率。

著录项

  • 公开/公告号DE4202623A1

    专利类型

  • 公开/公告日1992-09-03

    原文格式PDF

  • 申请/专利权人 MITSUBISHI DENKI K.K. TOKIO/TOKYO JP;

    申请/专利号DE19924202623

  • 发明设计人 MAENO HIDESHI ITAMI HYOGO JP;

    申请日1992-01-30

  • 分类号G01R31/318;G11C29/00;

  • 国家 DE

  • 入库时间 2022-08-22 05:25:26

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