Capacitive potential barrier semiconductor dynamic RAM - comprises matrix of word and bit lines interconnected by memory elements formed from potential barrier-gated capacitors

摘要

The memory device comprises a matrix of word/bit lines interconnected by a number of single-bit memory elements, each comprising two back-to-back diodes in series with a capacitor. The memory element matrix is constructed from a substrate of one doping type (1) with parallel rows of second doping type regions (3) that form discrete rows of electrodes. Every other row of electrodes (3b) forms a row of memory element lower capacitor lower plates, while the intermediate rows are connected to a metallic bit line. The other plate of the capacitor is formed from a strip of polycrystalline silicon (5) that also forms the word line and which is separated from the lower plate by an insulating layer (4). When a high potential is applied to the bit line conductor (8) while the word line conductor (5) is held low, charge flows across the electrode/substrate/electrode pn junctions and charges the lower plate of the capacitor, thus storing a logical ``1''. If the arrangement is reversed and a high potential is applied to the word line conductor while the bit line conductor is held low, a reverse charge flows, discharging the lower capacitor plate and storing a logical ``0''. ADVANTAGE - Lower memory element size results in increased memory density.