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Architecture of massively parallel computer system
Architecture of massively parallel computer system
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机译:大规模并行计算机系统的体系结构
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摘要
The description consists in disclosing an information-processing system architecture composed of an assembly of standard processors connected in parallel across DHWs (=BUSES), in the form of a two-dimensional matrix. The complete operational system can be composed of one or more elementary blocks (1024 blocks at most), each having at least 64 processors connected in the form of an 8 x 8 two-dimensional grid. The fundamental concept underlying this system is that of embracing within one hardware assembly the following three factors: - the use of conventional processors (industry standards) in large number, - the construction of rxr matrix-like connections (the example of a block with 64 processors is given by r = 8), - the use of parallel DHWs (data highways) as opposed to straightforward serial links. IMAGE
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机译:该描述在于公开一种信息处理系统架构,该信息处理系统架构由二维矩阵形式跨DHW(= BUSES)并行连接的标准处理器的组件组成。完整的操作系统可以由一个或多个基本块(最多1024个块)组成,每个基本块具有至少64个以8 x 8二维网格形式连接的处理器。该系统的基本概念是在一个硬件组件中包含以下三个因素:-大量使用常规处理器(行业标准),-构建类似rxr矩阵的连接(以64为例的块的示例)处理器由r = 8给出)-使用并行DHW(数据高速公路),而不是简单的串行链接。 <图像>
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