Circuit configuration for generating combinatorial binary logic functions with multiplexers and inverters

摘要

A circuit configuration for generating combinatorial logic functions includes a plurality of cascading circuit blocks, which are each formed of a 1-out-of-4 multiplexer and an inverter. Control inputs of the multiplexer are acted upon by input variables having a higher significance and data inputs are acted upon by a logical zero, a logical one, least significant input variables or inverted least significant input variables, in dependence on a linking function.