Timing control method in a common bus system having delay and phase correcting circuits for transferring data in synchronization and time division slot among a plurality of transferring units

摘要

In a common bus control method, transmission and reception buses are connected to a unit having a unit number 1. A synchronization frame head signal for time-division slots of common buses is sequentially supplied to the units in the order of the unit numbers 1 to n through delay circuits. Phase correcting circuits are respectively connected to the transmission and reception buses of each unit so as to perform phase correction of data on the buses and latch signals for latching the data. The delay circuit arranged in each unit sets transmission delay data having an inherent delay difference on the basis of the synchronization frame head signal. An output from the delay circuit of each unit is used as the latch signal.