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Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
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机译:用于逻辑电路设计综合过程的参数和规则创建与修改机制
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摘要
A logic method for automatically adding new parameters to a data base in a logic synthesis system. Initially, parameter definitions are input to the system and stored in a parameter definition table and used to create functions for accessing the parameter values associated with various components (model instances) in the data base. Both singular and plural access functions are generated for accessing single parameter values and lists of parameter values, respectively. A SETF function for modifying the parameter values is also generated from information in the parameter definition. Parameter values can be inherited from one model instance by another model instance. Each model instance in the data base has a dynamic parameter list associated therewith. Each dynamic parameter list contains entries of parameter name/value pairs. During circuit synthesis, the parameter values of various ones of these entries are modified using the SETF function, which was automatically generated previously. During circuit synthesis, certain model instances are deleted, to be replaced by certain other model instances. When a first model instance is replaced by a second model instance, all the parameter name/value pairs of "inheritable" parameters belonging to the dynamic parameter list of the first model instance are added to the dynamic parameter list of the second model instance. Thus, no information of inheritabel parameters is lost when a model instance is replaced.
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