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BUS RIGHT ARBITRATING CIRCUIT

机译:公交车右派电路

摘要

PURPOSE: To surely and previously prevent the generation of malfunction without using a software means by holding an access request only for a reaccess request delay time even when an access request to a resource connected to another private bus ends. ;CONSTITUTION: When a processor 1a tries to execute accessing processing continuously two times to a memory 3 connected to the private bus 2b of the other processor 1b in order to increase/decrease a data value, the access right of the bus 2b is not transferred to the processor 1b even when a fixed time exists between respective accessing processing and an access request signal (d) is reset within the fixed time when the time is less than the previously determined reaccess delay time. Since the processor 1b does not execute accessing processing to the memory 3 within the mutual accessing processing, data to be accessed by the processor 1a can be previously prevented from being accessed by the interruption of the processor 1b in error.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:为了确保并且以前不使用软件手段来防止故障的发生,即使在对连接到另一条专用总线的资源的访问请求结束时,也仅在重新访问请求延迟时间内保持访问请求。 ;组成:当处理器1a试图对连接到另一个处理器1b的专用总线2b的存储器3连续两次执行访问处理以增加/减少数据值时,总线2b的访问权限不会被转移即使在各个访问处理之间存在固定时间并且在该时间小于先前确定的重新访问延迟时间的情况下在该固定时间内重置访问请求信号(d)时,也可以向处理器1b发送信号。由于处理器1b在相互访问处理中不执行对存储器3的访问处理,因此可以通过处理器1b的错误中断而事先防止要被处理器1a访问的数据被访问。版权:(C) 1993,日本特许厅

著录项

  • 公开/公告号JPH05289987A

    专利类型

  • 公开/公告日1993-11-05

    原文格式PDF

  • 申请/专利权人 TOSHIBA CORP;

    申请/专利号JP19920091085

  • 发明设计人 SUMI KATSUHIRO;

    申请日1992-04-10

  • 分类号G06F13/362;

  • 国家 JP

  • 入库时间 2022-08-22 05:17:21

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