首页> 外国专利> CLOCK DISTRIBUTOR, CLOCK SIGNAL CORRECTION CIRCUIT, ELECTRONIC CIRCUIT SYSTEM, TWO-PHASE CLOCK GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MICROCOMPUTER

CLOCK DISTRIBUTOR, CLOCK SIGNAL CORRECTION CIRCUIT, ELECTRONIC CIRCUIT SYSTEM, TWO-PHASE CLOCK GENERATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MICROCOMPUTER

机译:时钟分配器,时钟信号校正电路,电子电路系统,两相时钟生成电路,半导体集成电路和微计算机

摘要

PURPOSE: To obtain high reliability even when a clock frequency is increased in a system including plural electronic circuits whose operating timings are controlled by two clock signals in which clock pulses are not superimposed. ;CONSTITUTION: Clock signal correction circuits 131, 132,... which generate the two clock signals 1n, 2n in which the clock pulses are not superimposed from two reference clock signals 1, 2 passing a clock transmission path are inserted between the clock transmission path and the electronic circuits 142, 142,... respectively. Thereby, it is possible to distribute the clock signal provided with an appropriate non-overlapping part to the electronic circuits 141, 142,..., which guarantees a stable operation even in a high clock frequency.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:即使在包括多个电子电路的系统中提高时钟频率时,也要获得较高的可靠性,该电子电路的工作时序由两个时钟信号控制,其中两个时钟信号未叠加。 ;组成:时钟信号校正电路131、132,...产生两个时钟信号1n,2n,其中时钟脉冲与通过时钟传输路径的两个参考时钟信号1、2不重叠电路142和142。由此,可以将具有适当的不重叠部分的时钟信号分配给电子电路141,142,...,即使在高时钟频率下也可以确保稳定的操作。(C)1993,日本特许厅

著录项

  • 公开/公告号JPH0546274A

    专利类型

  • 公开/公告日1993-02-26

    原文格式PDF

  • 申请/专利权人 HITACHI LTD;HITACHI VLSI ENG CORP;

    申请/专利号JP19920003812

  • 发明设计人 MASUMURA SHIGEKI;NAKAMURA HIDEO;

    申请日1992-01-13

  • 分类号G06F1/10;G06F1/06;G06F15/78;

  • 国家 JP

  • 入库时间 2022-08-22 05:14:18

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