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AMPLIFIER CIRCUIT FOR CMOS CRYSTAL OSCILLATOR CIRCUIT AND ITS USING METHOD

机译:CMOS晶体振荡器电路的放大器电路及其使用方法

摘要

PURPOSE:To correspond to both transmitting signal of a crystal oscillator circuit and clock signal of an external circuit by an amplifier circuit for a CMOS crystal oscillator circuit with simple constitution. CONSTITUTION:The gate terminal of respective MOS transistors 2 and 3 of a CMOS inverter circuit 1 is separated and connected to first and second respective independent external terminals A and B. The output terminal of the CMOS inverter circuit 1 is connected to an internal circuit and connected to a third external terminal C. When the oscillation signal of the crystal oscillator circuit is inputted to the internal circuit, the first and second external terminals A and B are mutually connected, and between the mutually connected common external terminals A and B and the third external terminal C, the crystal oscillator circuit is connected. On the other hand, when a clock signal is inputted to the above-mentioned internal circuit, the first and second external terminals A and B are respectively connected to off powers VDD and VSS to make each corresponding MOS transistor into an OFF condition and the clock signal is inputted to the third external terminal.
机译:目的:通过结构简单的CMOS晶体振荡器电路的放大器电路,既对应于晶体振荡器电路的发送信号,又对应于外部电路的时钟信号。组成:CMOS反相器电路1的各个MOS晶体管2和3的栅极端子分开,并分别连接到第一和第二各自独立的外部端子A和B。CMOS反相器电路1的输出端子连接到内部电路,并且当将晶体振荡器电路的振荡信号输入到内部电路时,第一和第二外部端子A和B相互连接,并且在相互连接的公共外部端子A和B与第二外部端子A和B之间。第三外部端子C,连接晶体振荡器电路。另一方面,当时钟信号输入到上述内部电路时,第一外部端子A和第二外部端子B分别连接到断开电源VDD和VSS,以使每个对应的MOS晶体管处于截止状态。信号输入到第三外部端子。

著录项

  • 公开/公告号JPH05136630A

    专利类型

  • 公开/公告日1993-06-01

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;FUJITSU VLSI LTD;

    申请/专利号JP19910295987

  • 发明设计人 MORITA HIROTAKA;

    申请日1991-11-12

  • 分类号H03B5/32;H03K19/0948;

  • 国家 JP

  • 入库时间 2022-08-22 05:13:54

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