CMOS INTEGRATED CIRCUIT FAN-IN LOGIC TREE LAYOUT ARRANGEMENT

摘要

A CMOS logic circuit, such as a crossbar digital switch, multistage multiplexer logic tree in a two-column compact folded layout of two columns, each having a width equal to a single stage of the tree, in order to minimize wiring delays and hence signal skew. Each stage of the tree, except for the first, includes a symmetrized two-input CMOS NAND gate followed in cascade by a symmetrized CMOS INVERTER gate, to minimize signal skew otherwise caused by the difference between pull-up and pull- down gate delays of CMOS gates and the skew otherwise caused by variations in semiconductor manufacturing processing conditions and variations in ambient operating conditions (temperature and power supply voltages). Also, a detailed delay balancing scheme separately for pull- up and pull-down gate delays is implemented along a pair of signal paths for generating each output signal and its simultaneous complement without relative skew between them. In this way a single-chip 64 input. times.17 output CMOS digital crossbar switch can be made to operate with date rates as high as 300 megabits per second.