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IN-LINE PIECE-WISE LINEAR DESYNCHRONIZER IN-LINE PIECE-WISE LINEAR DESYNCHRONIZER

机译:直插式明智的线性同步器直插式明智的线性同步器

摘要

PATENT 907-091 An in-line piece-wise linear desynchronizer eliminates the need for very low bandwidth analog, phase lock loops to smooth phase jumps caused by pointer changes such as those associated with a DS-1 signal mapped into a SONET VT 1.5 payload. The desynchronizer comprises a digital elastic store position detection circuit, a digital frame induced jitter filter, a digital leak rate filter, and a digital frequency synthesizer (VCO). The magnitude of the jitter can be reduced to any level by adjusting the digital VCO resolution and digital leak rate filter time constant. The desynchronizer produces a digitally synthesized output clock which can then be coupled to an analog/digital phase lock loop for smoothing high frequency jitter in the synthesized output clock, thereby providing an in-line interface function.
机译:专利907-091串联分段线性去同步器消除了对非常低带宽的模拟锁相环的需要,以平滑由指针变化(例如与映射到SONET VT 1.5有效负载的DS-1信号相关的指针)引起的相位跳变。去同步器包括数字弹性存储位置检测电路,数字帧感应抖动滤波器,数字泄漏率滤波器和数字频率合成器(VCO)。通过调节数字VCO分辨率和数字泄漏率滤波器的时间常数,可以将抖动的幅度降低到任何水平。去同步器产生一个数字合成的输出时钟,然后可以将其耦合到一个模拟/数字锁相环,以消除合成输出时钟中的高频抖动,从而提供一个在线接口功能。

著录项

  • 公开/公告号CA2079630A1

    专利类型

  • 公开/公告日1993-04-03

    原文格式PDF

  • 申请/专利权人 ALCATEL N.V.;

    申请/专利号CA19922079630

  • 发明设计人 WEEBER WILLIAM B.;

    申请日1992-10-01

  • 分类号H04L7/04;

  • 国家 CA

  • 入库时间 2022-08-22 05:08:30

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