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Detection circuit arrangement for faulty levels of digital signals injected in a bus

机译:用于检测总线中注入的数字信号电平错误的检测电路装置

摘要

The invention relates to a circuit arrangement for the detection of faulty levels of digital signals which are injected by at least one driver component, which is activated by data signals, into a bus line (15), wherein a decoupling unit is inserted between the relevant driver component and the bus line (15). For immediate detection of a functional fault in a driver component (13) and for identification of the latter, the output signal (A1) of each driver component (12, 52, 72) is combined in an exclusive-OR operation with the data signal (D1) to form an auxiliary signal (H), which is combined in an AND-operation with a release signal (E1) to form a fault signal (F1), which indicates a faulty level. IMAGE
机译:本发明涉及一种用于检测由至少一个由数据信号激活的驱动器部件注入到总线线路(15)中的数字信号的故障电平的电路装置,其中在相关部件之间插入去耦单元。驱动器组件和总线线路(15)。为了立即检测驱动器组件(13)中的功能故障并进行识别,将每个驱动器组件(12、52、72)的输出信号(A1)与数据信号进行异或运算(D1)形成辅助信号(H),在与操作中将其与释放信号(E1)组合在一起以形成指示故障电平的故障信号(F1)。 <图像>

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