Integrated circuit having reduced sensitivity to voltage transients

摘要

The invention relates to an input buffer (16) of an integrated circuit having a PMOS transistor (P1) and an NMOS transistor (N1) connected in series between first and second reference voltage terminals (V_DD, V_SS). A first filter (26) comprising a capacitor (C1) and a resistor (R1) is coupled between an input terminal (18), the first reference voltage terminal (V_DD) and the control electrode of the PMOS transistor (P1), and a second filter (28) comprising a capacitor (C2) and a resistor (R2) is coupled between the input terminal (18), the second reference voltage terminal (V_SS) and the control electrode of the NMOS transistor (N1). The filters (26, 28) act as low pass filters between the input terminal (18) and the control electrodes of the PMOS and NMOS transistors (P1, N1), and act as high pass filters between the reference voltage terminals (V_DD, V_SS) and the control electrodes. By virtue of the filters (26, 28), the input buffer (16) has reduced sensitivity to voltage transients on the reference voltage terminals (V_DD, V_SS).