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Efficiency improved DRAM row redundancy circuit
Efficiency improved DRAM row redundancy circuit
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机译:效率提高的DRAM行冗余电路
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摘要
A redundancy scheme for a memory is disclosed which allows defect correction, particularly, word line to word line short correction (40, 36, 38, 18) through the use of a minimal number of redundant lines (RWL0, RWL1).
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