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EFFICIENCY IMPROVED DRAM ROW REDUNDANCY CIRCUIT
EFFICIENCY IMPROVED DRAM ROW REDUNDANCY CIRCUIT
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机译:效率提高的DRAM行冗余电路
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摘要
Memory redundant structures have been described which can compensate for defects, in particular shorts between word lines, by using very few redundant word lines RWL 0 , RWL 1 .
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